a cmos jdc p /4 dqpsk baseband transmit port ad7010 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. general description the ad7010 is a complete low power, cmos, p /4 dqpsk modulator with single +5 v power supply. the part is designed to perform the baseband conversion of i and q transmit waveforms in accordance with the japanese digital cellular telephone system. the on-chip p /4 differential quadrature phase shift keying (dqpsk) digital modulator, which includes the root raised cosine filters, generates i and q data in response to the transmit data stream. the ad7010 also contains ramp control envelope logic to shape the i and q output waveforms when ramping up or down at the beginning or end of a transmit burst. besides providing all the necessary logic to perform p /4 dqpsk modulation, the part also provides reconstruction filters to smooth the dac outputs, providing continuous time analog outputs. the ad7010 generates differential analog outputs for both the i and q signals. as it is a necessity for all digital mobile systems to use the lowest possible power, the device has power down options. the ad7010 is housed in a space efficient 24-pin ssop (shrink small outline package). features single +5 v supply on-chip p /4 dqpsk modulator root-raised-cosine tx filters, a = 0.5 two 10-bit d/a converters 4th order reconstruction filters differential analog outputs on-chip ramp up/down power control on-chip tx offset calibration very low power dissipation, 30 mw typ power down mode < 5 m a on-chip voltage reference 24-pin ssop applications japanese digital cellular telephony functional block diagram tx clk bout qtx v aa mode1 ad7010 10-bit i-dac 2.46v reference power calibration circuitry p /4 dqpsk modulator 10-bit q-dac tx data dgnd v dd mode2 agnd bypass bin mclk ready reconstruction filters reconstruction filters itx itx qtx obsolete
rev. b C2C ad7010Cspecifications 1 (v aa = v dd = +5 v 6 10%; test = agnd = dgnd = 0 v; f mclk = 2.688 mhz; power = v dd . all specifications are t min to t max unless otherwise noted.) parameter ad7010ars units test conditions/comments digital mode transmit no. of channels 2 (itxC itx ) and (qtxC qtx ) output signal range v ref v ref /4 volts for each analog output differential output range v ref /2 volts i channel = (itxC itx ) and q channel = (qtxC qtx ) signal vector magnitude 2 0.875 7.5% volts max measured differentially error vector magnitude 2 1 % rms typ 2.5 % rms max offset vector magnitude 2 0.5 % typ 2.5 % max jdc spurious power 2, 3 @ 25 khz C30 db typ C25 db max @ 50 khz C60 db typ C55 db max @ 75 khz C70 db typ C65 db max @ 100 khz, 150 khz, 200 khz C70 db typ C65 db max reference & channel specifications reference, v ref 2.46 volts reference accuracy 5% i and q gain matching 0.2 db max measured @ 10 khz power down option yes power = 0 v logic inputs v inh , input high voltage v dd C0.9 v min v inl , input low voltage 0.9 v max i inh , input current 10 m a max c in , input capacitance 10 pf max logic outputs v oh , output high voltage v dd C0.4 v min |i out | 40 m a v ol , output low voltage 0.4 v max |i out | 1.6 ma power supplies v dd 4.5/5.5 v min/v max i dd transmit section active 8 ma max power = v dd 6 ma typ transmit section powered down 4 35 m a max mclk active 5 m a max mclk inactive notes 1 operating temperature ranges as follows: a version: C40 c to +85 c. 2 see terminology. 3 measured in continuous transmission and burst transmission with the i and q channels ramping up and down at the beginning and end of each burst. 4 measured while the digital inputs to the transmit interface are static and equal to 0 v or v dd . specifications subject to change without notice. ordering guide model temperature range package description package option ad7010ars C40 c to +85 c shrink small outline package rs-24 obsolete
ad7010 rev. b C3C 20k w 20k w 20pf 20pf ad7010 itx/qtx 40k w itx / qtx figure 1. analog output load test circuit q i modular output during ftest figure 2. modulator state during ftest master clock timing parameter limit at t a = C40 8 c to +85 8 c units description t 1 300 ns min mclk cycle time t 2 100 ns min mclk high time t 3 100 ns min mclk low time absolute maximum ratings* (t a = +25 c unless otherwise noted) v dd tx, v dd rx to agnd . . . . . . . . . . . . . . . C0.3 v to +7 v agnd to dgnd . . . . . . . . . . . . . . . . . . . . . C0.3 v to +0.3 v digital i/o voltage to dgnd . . . . . C0.3 v to v dd to + 0.3 v analog i/o voltage to agnd . . . . . . . C0.3 v to v dd + 0.3 v operating temperature range industrial (a version) . . . . . . . . . . . . . . . . C40 c to +85 c storage temperature range . . . . . . . . . . . . C65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . +150 c ssop q ja thermal impedance . . . . . . . . . . . . . . . . +122 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220 c *stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table i. mode 1 mode 2 operation 0 0 digital jdc mode 0 1 ftest 1 x factory test, reserved warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7010 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. (v aa = v dd = +5 v 6 10%; agnd = dgnd = o v. all specifications are t min to t max unless otherwise noted.) figure 3. master clock (mclk) timing figure 4. load circuit for digital outputs mclk t 2 t 1 t 3 to output pin +2.1v i oh c l 100pf 1.6ma 200 m a i ol obsolete
ad7010 rev. b C4C transmit section timing parameter limit at t a = C40 c to +85 c units description t 4 10 ns min power setup time. t 1 C 10 ns max t 5 4097t 1 + 70 ns max mclk rising edge, after power high, to ready rising edge. t 6 10 ns min bin setup time. t 1 C 10 ns max t 7 t 1 + 70 ns max mclk to ready low propagation delay. t 8 3t 1 + 70 ns mclk rising edge, after bin high, to first txclk rising edge. t 9 64t 1 ns txclk cycle time. t 10 32t 1 ns txclk high time. t 11 32t 1 ns txclk low time. t 12 50 ns min txclk falling edge to txdata setup time. t 13 0 ns min txclk falling edge to txdata hold time. t 14 3t 1 ns max bin low setup to last transmitted symbol after ramp down. t 15 124t 1 ns max bin low hold to last transmitted symbol after ramp down. t 16 7.5t 9 ns ramp down cycle time after the last transmitted symbol. t 17 30t 1 ns max last txclk falling edge to ready rising edge. t 18 10 ns max digital output rise time. t 19 10 ns max digital output fall time. mclk ready bin txclk txdata y k t 4 t 5 t 7 t 9 t 10 t 11 t 12 t 13 t 8 t 6 x k power figure 5. transmit timing at the start of a tx burst mclk ready bin txclk txdata t 14 x n+4 y n+4 x n+5 y n+8 x n+8 t 17 power t 15 t 16 figure 6. transmit timing at the end of a tx burst (v aa = v dd = +5 v 6 10%; agnd = dgnd = 0 v, f mclk = 2.688 mhz. all specifications are t min to t max unless otherwise noted.) obsolete
ad7010 rev. b C5C pin function description ssop pin number mnemonic function power supply 19 v aa positive power supply for analog section. 5v dd positive power supply for digital section, both supplies should be externally tied together. 14, 18, 23 agnd analog ground for transmit section. 6 dgnd digital ground for transmit section, both grounds should be externally tied together. analog signal and reference 13 bypass reference decoupling output. a decoupling capacitor should be connected between this pin a and agnd. 16, 17 itx, itx differential analog outputs for the i channel, representing true and complementary outputs of the i waveform. 21, 20 qtx, qtx differential analog outputs for the q channel, representing true and complementary outputs of the q waveform. transmit interface and control 7 mclk master clock, digital input. this pin should be driven by a 2.688 mhz cmos compatible clock source in digital mode. 3 txclk this is a digital output, transmit clock. this may be used to clock in transmit data at 42 khz. 4 txdata this is a digital input. this pin is used to clock in transmit data on the falling edge of txclk at a rate of 42 khz. 2 bin this is a digital input. this input is used to initiate the ramping up (bin high) or down (bin low) of the i and q waveforms. 24 bout burst out, digital output. this is the bin input delayed by the pipeline delay, both digital and analog, of the ad7010. this can be used to turn on and off the rf amplifiers in synchroniza- tion with the i and q waveforms. 1 power transmit sleep mode, digital input. when this goes low, the ad7010 goes into sleep mode, drawing minimal current. when this pin goes high, the ad7010 is brought out of sleep mode and initiates a self-calibration routine to eliminate the offset between itx & itx and the offset between qtx & qtx . 12 ready transmit ready, digital output. this output goes high once the self-calibration routine is complete. 9, 11 mode1, mode control, digital inputs. these are used to enter the ad7010 into three different mode2 operating modes, see table i. 8, 10, 15, 22 nc no connects. these pins are no connects and should not be used as routes for ot her circuit signals. ssop pin configuration power bin txclk txdata v dd dgnd mclk mode1 nc bout agnd qtx qtx v aa agnd itx itx agnd bypass 1 2 3 7 24 23 22 18 8 9 10 17 16 15 11 12 14 13 4 5 21 20 619 top view (not to scale) ad7010 nc mode2 ready nc nc obsolete
ad7010 rev. b C6C terminology error vector magnitude this is a measure of the rms error vector introduced by the ad7010 where signal error vector is defined as the rms devia- tion of a transmitted symbol from its ideal position, as illustrated in figure 7, when filtered by an ideal rrc filter. gain matching between channels this is the gain matching between the i and q outputs, mea- sured when transmitting all zeros. offset vector magnitude this is a measure of the offset vector introduced by the ad7010 as illustrated in figure 7. the offset vector is calculated so as to minimize the rms error vector for each of the constellation points. output signal range and differential output range the output signal range is the output voltage swing and dc bias level for each of the analog outputs. the differential output range is the difference between itx and itx for the i channel and the difference between qtx and qtx for the q channel. jdc spurious power this is the rms sum of the spurious power measured at multi- ples of 25 khz, in a rectangular window of 10.5 khz, relative to twice the rms power in a rrc window in the 0 khz to 10.5 khz band. signal vector magnitude this is the radius of the iq constellation diagram as illustrated in figure 7. i q error vector offset vector 0,0 signal vector figure 7. circuit description transmit section the transmit section of the ad7010 generates p /4 dqpsk i and q waveforms in accordance with jdc specification. this is accomplished by a digital p /4 dqpsk modulator, which in- cludes the root-raised cosine filters ( a = 0.5), followed by two 10-bit dacs and on-chip reconstruction filters. the p /4 dqpsk (differential quadrature phase shift keying) digital modulator generates 10-bit i and q data in response to the transmit data stream. the 10-bit i and q dacs are filtered by on-chip reconstruction filters, which also generate differential analog outputs for both i and q channels. p /4 dqpsk modulator the p /4 dqpsk modulator generates 10-bit i and q data (in- phase and quadrature) which are loaded into the i and q 10-bit transmit dacs. table ii. x k y k df k 1 1 C3 p /4 013 p /4 00 p /4 10C p /4 figure 8 shows the functional block diagram of the p /4 dqpsk modulator. the transmit serial data (txdata) is first con- verted into di-bit symbols [x k , y k ], using a 2-bit serial to paral- lel converter. the data is then differentially encoded; symbols are transmitted as changes in phase rather than absolute phases. each symbol represents a phase change, as illustrated in table ii, and this along with the previously transmitted symbol deter- mines the next symbol to be transmitted. the differential phase encoder generates i and q impulses [i k , q k ] in response to the di-bit symbols according to: i k = cos [ f k C1 + df k ] q k = sin [ f k C1 + df k ] differential phase encoder root-raised cosine filter i data q data 10 10 2-bit serial to parallel converter p /4 dqpsk digital modulator x k y k i k q k root-raised cosine filter txdata figure 8. p /4 dqpsk modulator functional block diagram figure 9 illustrates the p /4 dqpsk constellation diagram as de- scribed above, showing the eight possible states for [i k , q k ]. the i k and q k impulses are then filtered by fir root-raised cosine filters ( a = 0.5), generating 10-bit i and q data. the fir root-raised cosine filters have an impulse response of 4 symbols. i q figure 9. p /4 dqpsk constellation diagram transmit calibration when the transmit section is brought out of sleep mode (power high), the transmit section initiates a self-calibration routine to remove the offset between itx and itx and the offset between qtx and qtx . ready goes high on the completion of the self- calibration routine. once ready goes high, bin (burst in) can be brought high to initiate a transmit burst. obsolete
ad7010 rev. b C7C ramp-up/down envelope logic the ad7010 provides on-chip envelope shaping logic, providing power shaping control for the beginning and end of a transmit burst. when bin (burst in) is brought high, the modulator is reset to a transmitting all zeros state (i.e., x k = y k = 0) and continues to transmit all zeros for the first two symbols, during which the ramp-up envelope goes from zero to full scale as illus- trated in figure 10. the next symbol to be transmitted is [i 1 , q 1 ], which represents the first two data bits clocked in after bin going high, i.e., [x 1 , y 1 ]. 1 2 1 2 cos p t 2t 1 2 + 1 2 cos p t 2t 2 symbols 2 symbols figure 10. ramp envelope when bin is brought low, indicating the end of a transmit burst, the current di-bit symbol [x n+4 , y n+4 ] that the ad7010 is receiving will be the last symbol to be computed for the 4 symbol ramp-down sequence. also the n th symbol is the last active symbol prior to ramping down. however, because the impulse response is equal to 4 symbols, four additional symbols are required to fully compute the analog outputs when transmitting the (n+4) th symbol. hence there will be eight subsequent txclks, latching four additional di-bit symbols: [x n+5 , y n+5 ] to [x n+8 , x n+8 ]. as figure 11 illustrates, the ramp-down envelope reaches zero after two symbols, hence the third and fourth symbols do not actually get transmitted. reconstruction filters the reconstruction filters smooth the dac output signals, pro- viding continuous time i and q waveforms at the output pins. these are 4th order bessel low-pass filters with a C3 db fre- quency of approximately 22 khz, the frequency response is illustrated in figure 12. the filters are designed to have a linear phase response in the passband and due to the reconstruction filters being on-chip, the phase mismatch between the i and q transmit channels is kept to a minimum. 0 ?0 ?0 1 1000 100 10 0.1 ?0 ?0 ?0 ?0 ?0 ?0 frequency ?khz magnitude ?dbs figure 12. reconstruction filter frequency response for i and q dacs, mclk = 2.688 mhz transmit section digital interface mode1 = mode2 = dgnd: digital p /4 dqpsk mode figures 5 and 6 show the timing diagrams for the transmit interface when operating in jdc p /4 dqpsk mode. power is sampled on the rising edge of mclk. when power is brought high, the transmit section is brought out of sleep mode and ini- tiates a self-calibration routine as described above. once the self-calibration is complete, the ready signal goes high to indicate that a transmit burst can now begin. bin (burst in) is brought high to initiate a transmit burst and should only be brought high if the ready signal is already high. x 1 y 1 x n y n y n+1 x n+1 y n+2 x n+2 y n+3 x n+3 y n+4 x n+4 2 symbol ramp-up envelope 2 symbol ramp-down envelope i 1 q 1 i n q n i n+1 q n+1 i n+2 q n+2 i n+3 q n+3 i n+4 q n+4 0 0 0 0 symbol phase max effect bin txclk txdata bout (itx?tx), (qtx?tx) y n+5 x n+5 y n+6 x n+6 y n+7 x n+7 y n+8 x n+8 = 480 t 1 figure 11. transmit burst obsolete
ad7010 rev. b C8C c1779aC5C7/94 printed in u.s.a. i channel ?volts q channel ?volts 1.2 ?.2 1.2 0 ?.8 ?.8 ?.4 ?.2 0.8 0.4 0.8 0.4 0 ?.4 i channel ?volts q channel ?volts 1.2 ?.2 1.2 0 ?.8 ?.8 ?.4 ?.2 0.8 0.4 0.8 0.4 0 ?.4 figure 13. ad7010 i vs. q waveforms when transmitting random data i channel ?volts q channel ?volts 1.2 ?.2 1.2 0 ?.8 ?.8 ?.4 ?.2 0.8 0.4 0.8 0.4 0 ?.4 figure 14. ad7010 i vs. q waveforms filtered by an ideal root raised cosine receive filter when bin goes high, the ready signal goes low on the next rising edge of mclk and txclk becomes active after a further two mclk cycles. txclk can be used to clock out the trans- mit data from the asic or dsp on the rising edge of txclk and the ad7010 will latch txdata on the falling edge of txclk. when bin is brought low, the ad7010 will continue to clock in the current di-bit symbol (x n+4 , y n+4 ) and will continue for a further eight txclk cycles (four symbols). after the final txclk, ready goes high waiting for bin to be brought high to begin the next transmit burst. when power is brought low, this puts the transmit section into a low power sleep mode, drawing minimal current. the analog outputs go high impedance while in low power sleep mode. mode1 = dgnd; mode2 = v dd : frequency test mode a special ftest (frequency test) mode is provided for the customer, where no phase modulation takes place and the modulator outputs remain static. itx is set to zero and qtx is set to full scale as figure 2 illustrates. however, the normal ramp-up/down envelope is still applied during the beginning and end of a burst. mode 1 = v dd ; mode 2 = dgnd : factory test mode mode 1 = mode 2 = v dd : factory test mode these modes are reserved for factory test only and should not be used by the customer for correct device operation. i channel ?volts q channel ?volts 1.2 ?.2 1.2 0 ?.8 ?.8 ?.4 ?.2 0.8 0.4 0.8 0.4 0 ?.4 figure 15. ad7010 transmit constellation diagram i channel ?volts q channel ?volts 1.2 ?.2 1.2 0 ?.8 ?.8 ?.4 ?.2 0.8 0.4 0.8 0.4 0 ?.4 figure 16. ad7010 constellation diagram when filtered by an ideal root raised cosine receive filter outline dimensions dimensions are shown in inches and (mm). 24-lead ssop (rs-24) 1. lead no. 1 identified by a dot. 2. leads will be either tin plated or solder dipped in accordance with mil-m-38510 requirements 0.009 (0.229) 0.005 (0.127) 0.037 (0.94) 0.022 (0.559) 8 0 0.0256 (0.65) bsc 0.07 (1.78) 0.066 (1.67) 0.328 (8.33) 0.318 (8.08) 0.008 (0.203) 0.002 (0.050) pin 1 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.207) 1 24 13 12 obsolete
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